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Bipolar Transistor Structure

IP.com Disclosure Number: IPCOM000048778D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is disclosed to fabricate very compact transistors wherein both base and collector metal contacts are merely a submicron distance away from the emitter. The process sequence is preferably as follows: 1. Obtain the structure of Fig. 1 following a conventional basic process sequency up to the Si(3)N(4) deposition. 2. Form patterns in Si(3)N(4) layer 16 using a photoresist mask and RIE (reactive ion etch). Retaining the resist mask, ion implant a thin layer 18 of N+ impurity. 3. Through CVD (chemical vapor deposition), deposit approximately 8000 angstroms polysilicon 20 and approximately 800 A A Si(3)N(4) 22, this latter thickness being designed much much thinner than Si(3)N(4) layer 16 (Fig. 2). 4. Through photoresist masking and RIE, form patterns in Si(3)N(4) 22 and polysilicon 16 (Fig.

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Bipolar Transistor Structure

A method is disclosed to fabricate very compact transistors wherein both base and collector metal contacts are merely a submicron distance away from the emitter.

The process sequence is preferably as follows:
1. Obtain the structure of Fig. 1 following a conventional

basic process sequency up to the Si(3)N(4) deposition.
2. Form patterns in Si(3)N(4) layer 16 using a photoresist mask

and RIE (reactive ion etch). Retaining the resist mask, ion

implant a thin layer 18 of N+ impurity.
3. Through CVD (chemical vapor deposition), deposit approximately

8000 angstroms polysilicon 20 and approximately 800 A

A Si(3)N(4) 22, this latter thickness being designed much

much thinner than Si(3)N(4) layer 16 (Fig. 2).
4. Through photoresist masking and RIE, form patterns in

Si(3)N(4) 22 and polysilicon 16 (Fig. 3). Continuing RIE,

etch SiO(2) 12 and silicon to a depth a little below the

junction plane between N+ 18 and P 14 (Fig. 4).
5. Using a block-out photoresist mask 24, etch exposed silicon

a little below the interface of N- 8 and N+ 4 (Fig. 5).
6. Deposit approximately 5000 Angstroms pyrolytic SiO(2) 26,

and through vertical directional RIE, etch it

it away while retaining its portionsat the vertical sides

of the "pedestal" of Fig. 5 practically in

place. Grow thermal SiO(2)28 approximately 300 Angstroms in

thickness. As an option, a P implant may be done across

SiO(2)28, using ablock-out mask, in the extrinsic base

region. After a suitable drive-in heat cycle, the

cycle, the structure of Fig. 6 results.
7. Wet-etch away Si(3)N(4)22. (Si(3)N(4)16 gets only partially

removed because of its larger thickness.)
8. Wet-etch away polysilicon 20. Through dip-etch or RIE,

etch away thin SiO(2) 28 and 12 (Fig. 7).
9. Using a mask, wet-etch away portions of SiO(2) walls 26,

where desired, above Si(3)N...