Browse Prior Art Database

Delay Regulator DC Noise Assurance

IP.com Disclosure Number: IPCOM000048793D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+3]

Abstract

The disclosed technique assures DC noise margin for a delay regulated circuit.

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Delay Regulator DC Noise Assurance

The disclosed technique assures DC noise margin for a delay regulated circuit.

The delay regulation concept is described in the IBM Journal of Research and Development 25, 135-141 (May 1981).

The basic concept of delay regulation is placing special circuitry on each chip which will adjust the performance of all the logic gates on that chip by adding or removing power to the logic gates in order to obtain a performance dictated by an off-chip reference signal.

Fig. 1 shows a typical speed vs. power (i.e., delay vs. current source current) and typical tolerance curves for a current switch circuit. Using a power regulation scheme, there will be variations in chip-to-chip circuit delays due to manufacturing tolerances, etc., as shown by the power regulation operating point in Fig. 1.

Also shown in Fig. 1 is a typical delay regulation operating point. Selection of this point can be based on maximizing product yield or obtaining a specific delay. The method of selecting the typical delay regulation operating point is not important to this disclosure.

Fig. 1 shows there is product below the typical delay regulation operating line on the typical power regulation operating line, indicating this product is too fast. The delay regulation circuit will remove power from these circuits, causing them to move up the speed power curve to the typical delay regulation operating line. When power is removed from the fastest circuits, the circuits may not have sufficient noise margin. as shown in Fig. 1.

Although the following DC noise margin assurance circu...