Browse Prior Art Database

Layout For One Device FET Memory Cell

IP.com Disclosure Number: IPCOM000048796D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Baran, AS: AUTHOR [+7]

Abstract

The layout of a pair of one-device field-effect transistor (FET), memory cells is improved by eliminating sharp corners in the polysilicon one layer.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Layout For One Device FET Memory Cell

The layout of a pair of one-device field-effect transistor (FET), memory cells is improved by eliminating sharp corners in the polysilicon one layer.

Fig. 1 illustrates a known storage cell arrangement in which the entire semiconductor surface is covered by a first polysilicon layer (P0LY 1) except in the area designated as an opening. In this opening there is a "diffusion button", which is a doped region to which a bit line is subsequently connected. By means of the bit line (not shown) either storage plate 1 or storage plate 2 can be accessed depending on whether POLY 2 word line 1 or POLY 2 word line 2 is concurrently accessed.

It has been found that high stress corners 10 occur in the polysilicon where it is formed over field oxide or under the polysilicon 2 (POLY 2) layer. This weakness at the convex corners can result in POLY 1 to POLY 2 short circuits.

The aforementioned problems are avoided by the layout configuration of Fig. 2 in which the stress points (formerly at locations 10') are eliminated. The new opening in the POLY 1 has no convex corners. Although new straight line sections are shown, obviously other angles and curve configurations which avoid the convex corners would similarly solve this problem.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]