Browse Prior Art Database

Dummy Word Decoder

IP.com Disclosure Number: IPCOM000048797D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Mao, RS: AUTHOR [+2]

Abstract

This is a dummy word decoder with an active clamp for unselected dummy word lines.

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Dummy Word Decoder

This is a dummy word decoder with an active clamp for unselected dummy word lines.

In the operation of one-device (FET with capacitor storage) memory cells, it is known to use shared sense amplifiers and dummy cells. When using dummy cells, however, a decoder is required to perform the selection, balancing, and restoration of the dummy cell. The circuit diagram illustrated in Fig. 1 performs this function in accordance with the waveform diagram of Fig. 2.

Illustrated in Fig. 1 is a decoder and associated circuitry for dummy word line left (WDML1) and dummy word line right (WDMR1). It should be noted that on the second half of the chip there is another left dummy word line (WDML2) and another right dummy word line (WDMR2).

In the illustrated circuit, transistors T1, T2, T4, T5, T6 and T7 perform the cross-latch decoding. (The right dummy word line is controlled by the corresponding transistors noted in prime notation.)

The up level precharge signal (PR) precharges the bootstrap node at the source of T5 (and T5') to VDD minus VT (where VDD is the supply voltage and VT is the threshold voltage of the field-effect transistors). The word address (WO) signal at the gate of T6 and T6' determines whether the left or right dummy word line is to be selected. In the illustrated waveform diagram of Fig. 2, WO is brought to an up level, turning T6' on and T6 off.

Clock pulse RDE turns on the selected dummy cell, while the selected side precharge node active...