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Bit Driver And Select Circuit For Schottky Coupled Cell Arrays

IP.com Disclosure Number: IPCOM000048798D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Buscaglia, CU: AUTHOR [+2]

Abstract

The bit driver and select circuit shown in the figure meets Schottky coupled cell write requirements and is faster (for a given power) and requires less area than present bit driver circuits.

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Bit Driver And Select Circuit For Schottky Coupled Cell Arrays

The bit driver and select circuit shown in the figure meets Schottky coupled cell write requirements and is faster (for a given power) and requires less area than present bit driver circuits.

As shown in the figure, Ics is a "standard" current source (e.g., current mirror or equivalent). The DIN input is the data input from a data receiver. WBS is the write byte select input from the logic which controls which bits in the array are written. Vref is the current switch reference voltage.

With WBS in a "low" state (write mode), transistor T4 is "off" and one of the bit lines (left bit line LBL or right bit line RBL) is pulled up by either transistor T1 or transistor T2, resulting in writing a "1" or "0" in the selected cell (depending on the polarity of DIN).

With WBS higher than the most positive DIN level (inhibit mode), transistor T4 is "on", holding transistors T1 and T2 "off" through Schottky barrier diodes S3 and S4. With transistor T4 "on", transistors T3 and T5 are "off" and Schottky diodes S1 and S2 allow nodes 1 and 2 to rise to Vcc.

It can be seen from the above description that the design conditions for proper circuit function are IR1 equals IR3 equals Ics/2 and IR2 equals IR4 equals Ics/2 depending on whether transistor T3 or T5 is "on", which satisfies IR1 equals IR2 equals Ics/2 when transistor T4 is "on".

Although intended primarily as a bit driver for Schottky coupled cell arrays, the ar...