Browse Prior Art Database

Full Use of Transfer Cycles in Computers

IP.com Disclosure Number: IPCOM000048808D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

In the system-internal transfer networks of electronic data processing systems, central as well as decentral arbitration units are usually employed for assigning, according to priority, the transfer paths. i.e., generally the data bus, to the system components requesting such a transfer.

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Full Use of Transfer Cycles in Computers

In the system-internal transfer networks of electronic data processing systems, central as well as decentral arbitration units are usually employed for assigning, according to priority, the transfer paths. i.e., generally the data bus, to the system components requesting such a transfer.

The duration of the respective busy state of the data bus is indicated by a bus-busy signal. If several processing components request the data bus simultaneously by means of bus request signals, the arbitration unit decides, simultaneously with the execution of the current bus transfer, which processing component will be the next to which it will grant the bus. It is thus possible to grant the bus to the selected processing component by means of so-called grant signals immediately after the release of the bus. In this manner, the bus can be occupied uninterruptedly by the next bus transfer.

This time gap-free occupation of the data bus, however, can no longer be achieved with known transfer systems when the bus-busy times are very short, e.g., one bus clock cycle only. In order to achieve continuous bus occupation, with the aim of an optimum bus utilization, the arbitration unit receives, apart from the respective bus request signals, information as to whether the intended bus occupation is very slow. This communication can, e.g., be effected by transferring the respective bus command signal. On the strength of this information, the arbitration unit can activate the grant signal for the next processing components in time for its immediate allocation of the data bus.

However, if it is additionally to be expected that a short bus occupation of one clock cycle could be extended, e.g., through a refresh operation of a dynamic storage, such e situation is still reported by warning signals to the arbitration unit so that it can artificially delay the corresponding grant signals upon request.

Fig. 1 is a schematic representation of a processor consisting of processing component units I to IV, an arbitration unit, a data bus, as well as the control lines for the transfer of the control signals "bus request", "short cycle", as well as "refresh advance", "bus grant", and "bus busy".

Fig. 2 is a schematic representation of communication and control in such a system, with unit I transferring, in Example 1, a "bus request 1" without a "short cycl...