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Browse Prior Art Database

Refresh Control For Dynamic Ram

IP.com Disclosure Number: IPCOM000048830D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Higdon, JM: AUTHOR [+3]

Abstract

A refresh control for dynamic RAM (random-access memory) permits transparent refresh by coordinating refresh cycles with processor operation, but also limits the frequency of refresh cycles in accordance with the refresh requirements of the RAM itself.

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Refresh Control For Dynamic Ram

A refresh control for dynamic RAM (random-access memory) permits transparent refresh by coordinating refresh cycles with processor operation, but also limits the frequency of refresh cycles in accordance with the refresh requirements of the RAM itself.

To provide refresh that is transparent, refresh operation is alternated between two RAM banks and is permitted to occur during processor cycles in which the bank currently identified for refresh is not selected for a read or write operation by the processor. To limit the frequency of refresh, according to RAM refresh requirements, the time from the most recent refresh is accumulated and no further refresh cycle is initiated until the accumulated time exceeds a fixed period that is short or half the maximum allowable refresh separation interval by a preselected margin. By so controlling the spacing of refresh occurrences, each bank is always caused to be refreshed within the maximum allowable refresh interval.

Referring to Fig. 1, a circuit configuration for achieving alternating refresh of a first and a second bank of RAM (10 and 12) generates selection signals RM1SEL and RM2SEL at AND gates 14 and 16, respectively. The gates 14 and 16 are connected to receive address banks 10 and 12 is selected for a memory operation. One or more inverters 20 are used to condition the address signals at AND gates 14 and 16 to indicate when a corresponding bank 10 or 12 is selected for a memory operation. A further signal SELTIME is applied to the gates 14 and 16 from a clock 22 and i...