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Browse Prior Art Database

Differential Sense Amplifier For Unbalanced Data Lines

IP.com Disclosure Number: IPCOM000048831D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Tien, PC: AUTHOR

Abstract

The drawing shows a sensing arrangement in which the data lines have unbalanced capacitances because of manufacturing factors. To provide reliability the high data levels on the bit lines are positively charged to a full operating voltage level prior to transferring the data on the data lines to the second data sense circuit.

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Differential Sense Amplifier For Unbalanced Data Lines

The drawing shows a sensing arrangement in which the data lines have unbalanced capacitances because of manufacturing factors. To provide reliability the high data levels on the bit lines are positively charged to a full operating voltage level prior to transferring the data on the data lines to the second data sense circuit.

Dynamic random-access memories which have multibit outputs employ an off-chip driver and associated circuitry. In achieving optimized packaging density on a microcircuit chip, some unbalanced capacitive loading on the data lines may result. Such unbalanced loading is acceptable in this sensing arrangement, shown in the drawing with timing diagrams. CD and CDN are inherent capacitances of the data lines, which are different because of asymmetry in manufacture and design.

Signal PSAP is a bootstrapped clock that provides a precharge signal greater than a threshold voltage (V(TH)) above the power supply operating voltage V(DB) to equilibrate the nodes L1 and R1 through the precharge transistors T11 and T12. Bit line voltages VL2 and VR2 of nodes L2 and RZ are charged to V(DB) through depletion transistors T1 and T2. PSAP is brought to ground before a read or a write cycle starts.

Word line (WL) and dummy word line (WLD) are brought to a voltage level greater than a threshold voltage above V(DB). Charge redistribution among storage cell TCELL, dummy cell TDUMMY, and bit line capacitances CBLL and CBLR create a differential voltage between nodes L2 and R2 and between nodes L1 and R1.

PSA is then brought high. The voltage differential of nodes L1 and R1 guides the cross-coupled latch consisting of FETs T1, T2, T3, T4, T3A and T4A to set in a state dictated by the data stored in TCELL. Thus, when VL1 is slightly higher than VR1 as PSA is pulsing up, T4 and T4A are conducting harder than T3 and T3A. VR1 decreases toward ground level faster than VL1, making T3 and T3A less conductive. This voltage feedback action continues until VR1 drops to near ground level, turning off T3 and T3A while T4 and T4A are left heavily conducting. Consequently, shortly after PSA reach...