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Byte Synchronism Adjustment For Two SDLC Frames

IP.com Disclosure Number: IPCOM000048838D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Nelson, PE: AUTHOR [+2]

Abstract

There are times when it is necessary to synchronize Synchronous Data Link Control (SDLC) frames from two different sources, i.e., two SDLC frames where byte synchronism at the message level does not exist. For example, data synchronism on the loop systems must exist as data is propagated around the loop and each successive secondary station places its transmit data on the loop. If any data from a station is not in byte synchronism with data already on the loop, a second station downline from the one transmitting may start a transmission if seven one bits occur, thus blocking data from the upstream station not in byte synchronism.

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Byte Synchronism Adjustment For Two SDLC Frames

There are times when it is necessary to synchronize Synchronous Data Link Control (SDLC) frames from two different sources, i.e., two SDLC frames where byte synchronism at the message level does not exist. For example, data synchronism on the loop systems must exist as data is propagated around the loop and each successive secondary station places its transmit data on the loop. If any data from a station is not in byte synchronism with data already on the loop, a second station downline from the one transmitting may start a transmission if seven one bits occur, thus blocking data from the upstream station not in byte synchronism.

On all loops each communication adapter, which provides the interface between the loop and the data source, must place at least the leading zero of a first flag on the transmit data lead one-half bit time following the activation of the CTS (clear to send) signal. As loop speeds increase, it becomes more difficult and in some cases impossible to provide data within this one-half bit time. The number of bit times required will depend on the speed of the loop and the frequency of the oscillator providing the clocking.

This article describes a solution for the above problem. A flag inserter is provided in the loop signal converter and detection logic to determine when the leading zero of the flag from the attached communication adapter (CA) reaches the loop signal converter in relationship to the flag being inserted on the loop by the signal converter. The signal converter must then determine the byte synchronism point of these two data streams and adjust the terminal data stream to be in byte synchronism with the loop data or the flag which is being inserted by the signal converter. This byte synchronism point must be maintained for the duration of time the communication adapter is transmitting on the loop.

Fig. 1 shows a simplified loop signal converter with gates to block loop data in from passing to loop data out and to switch in the communication adapter data after detection of the loop go-ahead data sequence. Fig.2 shows a synchronizing shift register and the gating logic to provide synchronism between loop data in and loop data out.

In Fig. 1 the loop signal converter (SC) detects a unique go-ahead signal '01111111' and changes the seventh one bit to a zero, creating a new flag (byte synchronism) boundary on the loop. and enables the communication adapter (not shown) to transmit by activating the CTS signal. The SC follows the changed zero with a forced flag (01111110) and starts to look for the first zero bit from the CA. This first zero bit of the initial flag will establish the bit position at which the SC...