Browse Prior Art Database

Optimized Error Correction/ Detection For Chips Organized Other Than By-1

IP.com Disclosure Number: IPCOM000048843D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Cochran, WH: AUTHOR [+2]

Abstract

Granularity problems brought about by today's extremely dense memory chips and alpha-particle-induced soft errors are surfacing a requirement for single bit error correction with chips organized other than BY-1. Applying existing codes to BY-4 or BY-8 chips results in a drastic increase in undetected errors due to hardware failures. Double error detection is no longer sufficient. Since the chips each contain more than two bits, 3-, 4-and up to 8-bit errors become more prevalent.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Optimized Error Correction/ Detection For Chips Organized Other Than By- 1

Granularity problems brought about by today's extremely dense memory chips and alpha-particle-induced soft errors are surfacing a requirement for single bit error correction with chips organized other than BY-1. Applying existing codes to BY-4 or BY-8 chips results in a drastic increase in undetected errors due to hardware failures. Double error detection is no longer sufficient. Since the chips each contain more than two bits, 3-, 4-and up to 8-bit errors become more prevalent.

The present arrangement detects multiple-bit failures within a chip boundary 100 percent of the time and is applicable to any chip organization; however, examples will be limited to BY-4 chips or less. Additionally, mixing chip organizations within a word, e.g., BY-3 partial goods and BY-4, is possible with no loss in efficiency.

As an example, consider the IBM System/3 ECC (error correction code) for SEC/DED (single error correction/double error detection) with the following H- matrix: (see original)

If the above code is implemented with BY-3 chips, 3 out of a possible 7 3-bit errors are undetected (miscorrections at the following terms: 4 5 6/ 7 8 9/ 19 20
21). If implemented with BY-4 chips, 7 out of a possible 20 3-bit errors (1 3 4/ 5 6 8/ 9 11 12/ 13 14 16/ 17 18 20/ 17 19 20/ 18 19 20) are miscorrected, all 5 possible 4-bit errors are detected. Note that there are many more possible 3 and 4 bit errors within the 22-bit word (1540 possible 3-bit errors, 7315 possible 4-bit errors), but only 3-and 4-bit errors within a package boundary are considered.

By adding an additional check bit, the following code accomplishes 100 percent detection of all package failures when implemented with BY-3 or BY-4 chips, while maintaining full single error correction, double error detection: (see original)

If the above code is implemented with partial good chips where package boundaries align with a BY-3 or...