Browse Prior Art Database

Command Stacking For Microprocessor Controlled Channel Interface

IP.com Disclosure Number: IPCOM000048846D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Kerr, DJ: AUTHOR [+2]

Abstract

In Fig. 1, I/O controller (IOC) 20 controls more than one I/O device or operational unit (OU) 30. In the computer system shown in Fig. 1 there is no control unit busy response. The system is architected in a manner where it is assumed that IOC 20 will accept a command within a predetermined period of time. A problem arises with this architectural arrangement because IOC 20 may be busy with a command to one device 30 and be unable to handle another command to another device 30. Channel 15 normally waits for a response from IOC 20, but after waiting the predetermined time for the response and there is no response, it logs a time out error. In order to avoid this time out error and still be able to handle commands for more than one OU attached to the single IOC 20, channel bus 16 (Fig.

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Command Stacking For Microprocessor Controlled Channel Interface

In Fig. 1, I/O controller (IOC) 20 controls more than one I/O device or operational unit (OU) 30. In the computer system shown in Fig. 1 there is no control unit busy response. The system is architected in a manner where it is assumed that IOC 20 will accept a command within a predetermined period of time. A problem arises with this architectural arrangement because IOC 20 may be busy with a command to one device 30 and be unable to handle another command to another device 30. Channel 15 normally waits for a response from IOC 20, but after waiting the predetermined time for the response and there is no response, it logs a time out error. In order to avoid this time out error and still be able to handle commands for more than one OU attached to the single IOC 20, channel bus 16 (Fig. 2) transfers the identity or OU number of the device being commanded. This number is entered into register 21 and decoded by decode 22 to generate an OU identity signal which IOC 20 can recognize. The signal from decode 22, representing either a start device or halt device command, sets a corresponding bit in hardware stack 23. A halt device command uses the same channel sequence as is used for a start device command except that the halt interface line from the channel is also active.

Stack 23 allows the microcode executed by IOC 20 to process a command for one OU while additional commands can be accepted for other OUs a...