Browse Prior Art Database

Direct Cycle Steal Between Remotely Attached I/O Device And System Processor

IP.com Disclosure Number: IPCOM000048847D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Beukema, BL: AUTHOR [+2]

Abstract

When it is desired to improve performance on a system with a single processor, it often becomes necessary to offload work by adding I/O processors to control the I/O devices. However, certain I/O devices (e.g., disks, diskettes, and tape drives) are frequently required to transfer large blocks of data to the system processor. For these types of devices, the advantages of a multiprocessing system are greatly reduced, since to transfer data to the system processor, the I/O device must first transfer its data to the I/O processor and then from the I/O proprocessor to the system processor. This results in having the same data transferred twice, and also inhibits the I/O processor from doing any work for the duration of both transfers.

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Direct Cycle Steal Between Remotely Attached I/O Device And System Processor

When it is desired to improve performance on a system with a single processor, it often becomes necessary to offload work by adding I/O processors to control the I/O devices. However, certain I/O devices (e.g., disks, diskettes, and tape drives) are frequently required to transfer large blocks of data to the system processor.

For these types of devices, the advantages of a multiprocessing system are greatly reduced, since to transfer data to the system processor, the I/O device must first transfer its data to the I/O processor and then from the I/O proprocessor to the system processor. This results in having the same data transferred twice, and also inhibits the I/O processor from doing any work for the duration of both transfers.

The present arrangement includes direct cycle stealing through a bus coupler to eliminate these data transfer problems.

The bus coupler 20 (Fig. 1) is a device which attaches between the system channel 15 and an I/O channel 30 and functions to allow communication between system processor 10 and an I/O processor 50. For each I/O processor 50, there is associated a corresponding bus coupler 20. Fig 1 shows a maximum of Z bus coupler/I/O processor pairs that can be attached to system processor 10 via the system channel 15 and a maximum of N I/O devices 70 which can be attached to each I/O processor 50 via I/O channel 30. Also shown in Fig. 1 are "Direct Cycle Steal Request" signal lines 80 connecting the I/O devices 70 to a corresponding bus coupler 20.

Bus couplers 20 are designed such that they can either drive or receive the control lines of the I/O channel 30. However, the I/O processors can only drive these control lines, and the I/O devices 70 can only receive them.

The following sequence of events occur during a "Direct Cycle Steal". When a remotely-attached I/O device 70 wishes to do a "Direct Cycle Steal", it raises the "Direct Cycle Steal Request" line 80 to the associated bus coupler 20. Up to N remotely-attached I/O devices 70 may request a "Direct Cycle Steal" simultaneously. Bus coupler 20 synchronizes the "Direct Cycle Steal Request" line 80 with a signal from the I/O processor 50, called "I/O Channel Available" on line 51 (Fig. 2). The signal "I/O Channel Available" tells bus coupler 20 that the I/O processor 50 is not driving the I/O channel 30 (i.e., not performing I/O instructions or cycle steals).

The two signals "Direct Cycle Steal Request" and "I/O Channel Available" are applied to AND circuit 21, and its output is connected to set I/O Channel Busy latch 25. When latch 25 is set, the "I/O Channel Busy" signal inhibits the I/O processor 50 from driving the I/O channel 30 (i.e., performing I/O instructions or cycle steals). The "I/O Channel Busy" and "Direct Cycle Steal Request" lines 26 and 80 are applied to AND circuit 27 to activate the "System Base Cycle Steal Request" line 28 to system processor 10. Thus, t...