Browse Prior Art Database

Automatic Channel Request For Data Transfers

IP.com Disclosure Number: IPCOM000048848D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Havelick, GW: AUTHOR [+2]

Abstract

When an I/O device 20 (Fig. 1) is transferring data to central processing unit (CPU) 10 via channel 15. it transfers the data to data store 50 under direct memory access control. Microprocessor 40 executes microcode for detecting when a large block of data is contained in data store 50. Upon detecting the large block of data in data store 50, the microcode requests a transfer of this data to the channel 15 via channel interface circuitry 60. The channel interface circuitry 60 transfers the data from data store 50 to system channel 15 at the same time that device 20 continues to store more data in data store 50. The microcode then requests another channel transfer upon detecting that another block of data has been entered into data store 50.

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Automatic Channel Request For Data Transfers

When an I/O device 20 (Fig. 1) is transferring data to central processing unit (CPU) 10 via channel 15. it transfers the data to data store 50 under direct memory access control. Microprocessor 40 executes microcode for detecting when a large block of data is contained in data store 50. Upon detecting the large block of data in data store 50, the microcode requests a transfer of this data to the channel 15 via channel interface circuitry 60. The channel interface circuitry 60 transfers the data from data store 50 to system channel 15 at the same time that device 20 continues to store more data in data store 50. The microcode then requests another channel transfer upon detecting that another block of data has been entered into data store 50.

For optimum device performance in transferring large amounts of data, the data block size should be large so as to reduce the number of times the microcode must intervene to transfer the data. Normally, the larger the block size the larger the data store required to buffer the data until it is transferred to the system channel. The present arrangement which provides for an automatic channel request reduces the data store size requirements and also the amount of microcode for performing the data transfer. Data store 50 in Fig. 2 is partitioned into buffers which are addressed by addresses in device data address register 70 and by addresses in channel data address register 75. When data is to be transferred from I/O device 20 to channel 15, the microcode in microprocessor 40 sets automatic request latch 78, loads buffer number register 85 with the number of buffers allocated in data store 50, and sets transfer request latch 100.

As data is entered into data store 50 from I/O device 20 in positions addressed by the address in register 70, it fills buffer 51 and thereafter starts to fill buffer 52. When the address in register 70 crosses the buffer boundary between buffers 51 and 52, a crossing condition is detected by logic block 71 which generates a signal passed by gating 77 to increment buffer counter 80. Logic block 81 detects that counter 80 is no longer equal to zero and it passes a signal via...