Browse Prior Art Database

Improved Tagged Pointer Verification

IP.com Disclosure Number: IPCOM000048849D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Thomforde, DJ: AUTHOR

Abstract

Tagged pointer verification is described in U.S. Patent 4,241,396. This patent describes a pointer as a quad-word in storage which contains, among other things, a 6-byte address for pointing to a particular byte or number of bytes within a storage space. The tagged pointers are mixed with data, and thus it is desirable to check and verify the validity of pinters without affecting the performace and operation of other instructions. Each word in main storage has a tag bit. Only tag instructions can set the tag bits on. All data handling instructions set the corresponding tag bits off. Thus, if a pointer were modified inadvertently by one of the data handling instructions, that can be detected by examining the tag bits of the pointer.

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Improved Tagged Pointer Verification

Tagged pointer verification is described in U.S. Patent 4,241,396. This patent describes a pointer as a quad-word in storage which contains, among other things, a 6-byte address for pointing to a particular byte or number of bytes within a storage space. The tagged pointers are mixed with data, and thus it is desirable to check and verify the validity of pinters without affecting the performace and operation of other instructions. Each word in main storage has a tag bit. Only tag instructions can set the tag bits on. All data handling instructions set the corresponding tag bits off. Thus, if a pointer were modified inadvertently by one of the data handling instructions, that can be detected by examining the tag bits of the pointer.

As described in the referenced patent, main storage accesses are alternated between SA and SB registers, as illustrated in Fig. 1A herein. The tag bits in the referenced patent were stored in SA tag bit and SB tag bit latches as in Fig. 2 thereof. Thus, to avoid losing the tag data for the first eight bytes fetched, it was necessary to check the state of the tag bit latches before fetching the next 8 bytes of the quad-word. This testing was accomplished by an instruction *=V3(XR) '03' at clock time 36. If both the SA tag bits were on, this instruction struction sets another latch and an instruction branch is made on the state of this other latch. If this other latch is in the reset state, a verify exception is raised and the processing of the instruction i...