Browse Prior Art Database

Improved Data Handling

IP.com Disclosure Number: IPCOM000048851D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Jones, ER: AUTHOR [+2]

Abstract

Data handling in a computer system having a microprocessor of the type shown in the IBM Technical Disclosure Bulletin 22, 2054-2059 (October 1979) can be improved by adding a data path, lookahead fetch logic and otherwise using existent registers to fullest advantage. In the referenced publication, no data path existed from the SB L2 register to the arithmetic and logic unit (ALU). In Fig. 1 herein, the SDR A and SDR B registers 20 and 25 are the same as in the referenced publication. The SDR A L1 latches however have the reference character 21 and the SDR A L2 latches have the reference character 22. Similarly, the SDR B register 25 has the SDR B L1 and the SDR B L2 latches referred to by reference characters 26 and 27, respectively.

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Improved Data Handling

Data handling in a computer system having a microprocessor of the type shown in the IBM Technical Disclosure Bulletin 22, 2054-2059 (October 1979) can be improved by adding a data path, lookahead fetch logic and otherwise using existent registers to fullest advantage. In the referenced publication, no data path existed from the SB L2 register to the arithmetic and logic unit (ALU). In Fig. 1 herein, the SDR A and SDR B registers 20 and 25 are the same as in the referenced publication. The SDR A L1 latches however have the reference character 21 and the SDR A L2 latches have the reference character 22. Similarly, the SDR B register 25 has the SDR B L1 and the SDR B L2 latches referred to by reference characters 26 and 27, respectively. By adding a path from SDR B L2 latches 27 to ALU 40, data can be transferred from SDR B L2 27 into SDR A L1 21. This particular data path provides a performance improvement during several basic computer operations such as during arithmetic operations, movement of data from registers, and movement of data from one location to another location in storage.

When data is to be moved from one location in storage 10 (Fig. 1) to another location therein, the data in the destination field must be fetched to a processor register and, in this instance, SDR A L1 21 so that adjacent data is not destroyed in the event the field does not start on a full word boundary or the field is less than a full word in length. This fetch operation is represented by block 01 in Fig.
2. Source data is then fetched from the source field in main storage 10 and entered into source data register SDR B L1 26, as represented by block 02 (Fig.
2). Since the source data field may be greater than the amount of data which can be transferred from main storage 10 to SDR B L1 26 in a single storage access, a test is made for such a condition, as represented by block 03 in Fig. 2. If there is no more additional source data, the data in the SDRB L1 26 can be transferred to SDR B L1 27 by block 11 and the data movement can be initiated whereby data is transferred from SDR B 25 to SDR A 20 and more particularly from SDR B L2 27 to SDR A L1 21 one byte at a time. This data movement operation is represented by block 05 in Fig. 2. Once the entire contents of SDR B L2 27 are moved into SDR A L1 21, as determined by block 06 in Fig. 2, the data in SDR A 20 is transferred to main storage 10 as represented by block 07.

If more source data is needed as determined by block 03, a look ahead fetch is made where data is fetched...