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Code Sharing By Functions Having Different Addressing Requirements

IP.com Disclosure Number: IPCOM000048852D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Goolsbey, MA: AUTHOR [+2]

Abstract

In a computer system such as the IBM System/38, microprogramming is used to execute another level of instructions which include a highly used instruction. The microcode for executing the highly used instruction is optimized for performance reasons and does not permit a check point restart for lookaside buffer misses which can occur in a virtual storage system. The microcode for executing the highly used instruction includes microcode which can be shared for execution of other instructions that must be check point restarted on lookaside buffer misses. This imposes a problem of handling the lookaside buffer misses without impacting the performance of the highly used instruction. Check point return control information is passed as a return address in a dedicated LSR (local storage register) LBMC (lookaside buffer miss control).

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Code Sharing By Functions Having Different Addressing Requirements

In a computer system such as the IBM System/38, microprogramming is used to execute another level of instructions which include a highly used instruction. The microcode for executing the highly used instruction is optimized for performance reasons and does not permit a check point restart for lookaside buffer misses which can occur in a virtual storage system. The microcode for executing the highly used instruction includes microcode which can be shared for execution of other instructions that must be check point restarted on lookaside buffer misses. This imposes a problem of handling the lookaside buffer misses without impacting the performance of the highly used instruction. Check point return control information is passed as a return address in a dedicated LSR (local storage register) LBMC (lookaside buffer miss control). The contents of this register are normally the default condition of zero to indicate that the instruction is not check point restarted. If a check point restart is performed, the LBMC register is loaded with the check point return address from a control word prior to the control word, which can incur a lookaside buffer miss. This problem is solved by placing the lookaside buffer miss code not in line with the common code and providing entry into the common code from either the existing entry point or a point internal to the common code.

In the drawing, common code 20 is entered by the high use instruction at point 25. Other instructions using common code 20 that are check point restarted on lookaside buffer misses enter the common code at point 25 via control words 9 and 10. Control word 9 functions...