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NRZI Double Pulse Code Conversion

IP.com Disclosure Number: IPCOM000048868D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Bailey, JA: AUTHOR

Abstract

Fig. 1 is a diagram of a prior-art method for NRZI to pulse code conversion. The adder is a three-input exclusive OR gate. Each rectangle represents a unit delay. P/t/ is the first pulse of each period. Q/t/ is the second.

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NRZI Double Pulse Code Conversion

Fig. 1 is a diagram of a prior-art method for NRZI to pulse code conversion. The adder is a three-input exclusive OR gate. Each rectangle represents a unit delay. P/t/ is the first pulse of each period. Q/t/ is the second.

By allowing a 1/2-cycle shift in the outputs, the Fig. 1 diagram can be greatly simplified. A simplified implementation for a code converter for a single track is shown in Fig. 2. The simplification is realized by accepting a 1/2-cycle phase shift in the output pulses, as shown in Fig. 3.

A multi-track implementation with a data demultiplexer and the necessary timing circuits is illustrated in Fig. 4, with an accompanying pulse diagram shown in Fig. 5.

The shift register serves to generate 1/12 duty-cycle pulses--u, v, w...u', v', w'...z'. The pulses from the shift register are gated with the true and complement outputs from the LATCH. A +pulse is generated when either of the following two conditions exist: (1) u and DATA1 or (2) u' and DATA1. A negative pulse is generated when either of the following two conditions exist: (1) u and DATA1 or
(2) u' and DATA1.

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