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Write Current Shaping Circuit For Magnetic Recording

IP.com Disclosure Number: IPCOM000048872D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Hartung, JC: AUTHOR [+2]

Abstract

The undesirable peak shift generated in digital recording channels is one of the most critical obstacles to high density recording. In previous tape drives a method of peak shift correction was implemented which is characterized as write channel equalization. The method involves shaping the write current waveform of each channel such that every transition in the waveform is followed by a minor transition of opposite polarity. The previously utilized circuit to implement this technique, however, required the use of two single-shot multivibrators for each track.

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Write Current Shaping Circuit For Magnetic Recording

The undesirable peak shift generated in digital recording channels is one of the most critical obstacles to high density recording. In previous tape drives a method of peak shift correction was implemented which is characterized as write channel equalization. The method involves shaping the write current waveform of each channel such that every transition in the waveform is followed by a minor transition of opposite polarity. The previously utilized circuit to implement this technique, however, required the use of two single-shot multivibrators for each track.

In the figure, a circuit is illustrated which generates required compensation currents for each track in a nine-track set with only one single-shot multivibrator. The generated compensation currents are added to the corresponding data currents in the usual fashion, resulting in the desired minor transitions of both polarities.

In the circuit illustrated, the single-shot multivibrator is triggered at each data transition of either polarity. The single-shot multivibrator output serves as a clock input to a corresponding D latch flip-flop (D-FF) for each track. The D-FF output and the corresponding data are gated through the illustrated logic circuits to switch two transistor output stages, one for each compensation current, positive or negative. Consequently the desired compensation currents are created with a much less expensive circuit configuration than...