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Masking Peripheral Interrupts

IP.com Disclosure Number: IPCOM000048874D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Beardsley, BC: AUTHOR [+4]

Abstract

A Programmable Logic Array (PLa) is interposed between a device controller and a controller receives interrupts from the devices and identifies the devices on a bit significant basis. A poll signal from the control unit transfers the contents of the device controller's register to the PLA for masking operations. The control unit selectably sets the mask in the PLA such that interrupts only from selected devices reach the control unit.

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Masking Peripheral Interrupts

A Programmable Logic Array (PLa) is interposed between a device controller and a controller receives interrupts from the devices and identifies the devices on a bit significant basis. A poll signal from the control unit transfers the contents of the device controller's register to the PLA for masking operations. The control unit selectably sets the mask in the PLA such that interrupts only from selected devices reach the control unit.

The control unit operates with a plurality of devices through one or more device controllers. Data is transferred from a host through a channel to the control unit and thence to the devices. Since a control unit has a microprocessor (not shown) for operating the peripheral system, it is desired for time dependent operations to prevent certain devices from interrupting the control unit. This is achieved by a two step process. Each device controller has a register which receives interrupts or attention requests from its attached devices. The device is identified by the bit positions in the register. In this manner, attention and device interrupts are memorized by the device controller.

When the control unit wishes to service an interrupt from a device, it polls the register. i.e., causes the contents of the register to be transferred to a PLA. The PLA contains the register having a mask of bits for acceptable and rejectable interrupts. The mask is set by the control unit microprocessor. The contents of th...