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Non-Precharging Scheme For Speed-Up In MOS Circuit In Multiphased Clock Systems

IP.com Disclosure Number: IPCOM000048884D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Miranker, GS: AUTHOR

Abstract

An architectural scheme for increasing the time high, or one, levels have to propagate in clocked MOS/VLSI systems is presented. This scheme is similar to precharging but avoids (Delta)I problems.

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Non-Precharging Scheme For Speed-Up In MOS Circuit In Multiphased Clock Systems

An architectural scheme for increasing the time high, or one, levels have to propagate in clocked MOS/VLSI systems is presented. This scheme is similar to precharging but avoids (Delta)I problems.

Ratioed MOS logic suffers in speed performance because of the limited current capability of pull-ups. An inverter with a (Beta) ratio of k will have a rise- to-fall time of about k.

In multiphase clocked systems this problem is alleviated using precharging. However, precharging places large loads on the clock lines and thus is noisy. This article shows how the speed advantage of precharge can be obtained without its problems of noise.

For example, consider the circuit of Fig. 1, where C(L) is large.

For correct operation the delay from a to b, Tab, must be less than the interval from the falling edge of (Phi)(1) to the falling edge of (Phi) (2), T, assuming a minimum clock time for (Phi)(1) and (Phi)(2).

Suppose a single device is added, as shown in Fig. 2.

Now point C is forced low, and hence node b goes high during (Phi) (1). Thus, a zero must still propagate in time T; however, a one has from the rising edge of (Phi)(1) to the trailing edge of (Phi)(2), or T + T (on(Phi)(1)), when T(on(Phi)(1)) is the width of pulse (Phi)(1). Thus, one propagation (the slow direction) has an additional time that typically ranges from 1/4T to 1/2T.

This scheme is only suitable in clocked systems. It has mu...