Browse Prior Art Database

Creation of Super Instructions In Hardware

IP.com Disclosure Number: IPCOM000048893D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Agerwala, TK: AUTHOR [+5]

Abstract

High performance processors like the IBM System/370 Model 3033 use a hardwired instruction preprocessing function unit (IPPE) and microcoded execution (E) unit. An ideal instruction goes through the pipelined lined machine in four cycles as follows: In the first cycle (D/A), the instruction is decoded to determine the needs in terms of general purpose registers (GPRs) and operands from cache, and information relevant to its execution activity is placed in a four-position queue between the IPPF and the E unit. In the next cycle (C1), the operand access for the instruction if any is begun.

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Creation of Super Instructions In Hardware

High performance processors like the IBM System/370 Model 3033 use a hardwired instruction preprocessing function unit (IPPE) and microcoded execution (E) unit. An ideal instruction goes through the pipelined lined machine in four cycles as follows: In the first cycle (D/A), the instruction is decoded to determine the needs in terms of general purpose registers (GPRs) and operands from cache, and information relevant to its execution activity is placed in a four- position queue between the IPPF and the E unit. In the next cycle (C1), the operand access for the instruction if any is begun. In the third cycle (C2), the operand arrives from the cache (assuming a hit in the cache) while the micro- instruction to execute the instruction is read out of control storage and the working registers in the E unit are set up in preparation of the execution of the instruction. The instruction is executed in the next cycle (E), and the results are put away in the follwing cycle.

In general, instructions processed by the CPU are dependent on each other. The design of both the instruction (I) unit and the E unit implicitly recognizes such dependence to speed up the processing of instructions. The Load Bypass is an example of such a mechanism in the I unit, while the Wrap to A register and Wrap to B register serve a similar purpose in the E Unit.

The purpose here is to disclose a mechanism that explicitly recognizes when certain frequent, mutually dependent instructions are processed by the I unit, creates a 'super instruction' that does the same work as the instruction sequence it replaces, and executes the super instruction in the E unit in a fewer number of cycles than the original instruction sequence. For some pairs this is accomplished without changes in the E unit except for changes in microcode.

There is no change in the sequence or number of instructions processed by the I unit or the number of cycles taken by the I unit.

For some pairs there is no change in the total amount of work done by the E unit or the sequence in which it is done (except that it is done in fewer cycles). Thus, there should be no problems with architecture specified orders or instruction retry.

The concept is illustrated below in the context of a frequent pair of instructions: (TM, BC(R)), where TM is Test under Mask and BC is Branch on Condition, though it will work equally well for (CLI BC(R)), (LTR BC(R)), and other pairs. :BC is decoded, then a super-instruction can replace the instruction sequence (TM, BC). This is done by reading out a micro-instruction(s) that corresponds to the super-instruction rather than just the TM. The :BC Successful signal is generated during the execution cycle of the TM instruction (early generation of BC Successful); thus, the execution cycle of the BC is a null cycle. Thus, in this case the super-instruction corresponds to a micro-instruction sequence that does the work currently being done...