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# Switching Circuit Timing Verification

IP.com Disclosure Number: IPCOM000048894D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 36K

IBM

## Related People

Kurtzberg, JM: AUTHOR [+2]

## Abstract

The correctness of the timing is important in the technology of static field-effect transistors (FETs). Herein is provided an algorithm for timing determination in this technology.

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Switching Circuit Timing Verification

The correctness of the timing is important in the technology of static field- effect transistors (FETs). Herein is provided an algorithm for timing determination in this technology.

As a model for static FET switching designs a contact network such as is shown in the figure is utilized. The problem is to determine the longest acyclic path in time from a to i. It is assumed that the delays of the transistors are all equal. This being assumed, the longest paths in time are the longest acyclic paths.

The following procedure is a method for finding the longest acyclic paths. Label the initially chosen terminal node as 1. Label all nodes immediately adjacent to it as 2. Having labelled all nodes of length i or less from a by multiple labels, label all nodes adjacent to the maximally labelled node, if the maximal label thus far is k, with the label k+i; add this label to the labels of these adjacent nodes provided only that no cycles are introduced.

The test for cyclicity is simple: a sequence of nodes beginning and ending with a given node and in the sequence of the delay-number assignments is strictly ascending.

The maximal path is obtained by "walking" back from the first terminal node c, it having been labelled by the process to the terminal node a.

In the example, two paths of length 9 are determined: one, a,b, d,g,e,c,f,h,i and the other, a,c,f,h,e,b,d,g,i.

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