Browse Prior Art Database

High Speed Multiplexing Of Characters

IP.com Disclosure Number: IPCOM000048897D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

McVey, JM: AUTHOR [+3]

Abstract

In word processing applications, it is often desirable to provide a full page CRT display; however, the character display rate for a full page CRT adapter design usually requires a high speed ROM (read-only memory) character generator. Such high speed ROMs are expensive and not readily available.

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High Speed Multiplexing Of Characters

In word processing applications, it is often desirable to provide a full page CRT display; however, the character display rate for a full page CRT adapter design usually requires a high speed ROM (read-only memory) character generator. Such high speed ROMs are expensive and not readily available.

The circuit shown in Fig. 1 employs four slow, readily available ROM modules, the outputs of which are multiplexed at high speed. Each of the four character generators contains the same character font information and fetches scan row information for one of each group of four characters. This allows the effective character time seen by each character generator to be four times longer than in a single fetch implementation. Data from each character generator is latched externally to the device to allow pipelining of the character stream for high speed operation. As shown in Fig. 2, the timing of this logic is designed such that data from all four latches has been loaded into the shift register before the next access from the character generators is complete. The character scan row information from the character generators is fed to the shift register through the four to one data path at a rate compatible with the display scan time.

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