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Multiprocessor Packet Switching Memory and I/O Channel

IP.com Disclosure Number: IPCOM000048898D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Vrba, RA: AUTHOR

Abstract

A multiprocessor system with a conventional interconnecting channel achieves much less performance than the same number of processors used in separate uniprocessor systems. This is because a typical processor can use almost the entire bandwidth of the channel and starve any other processors tied to it. This limitation can be overcome by adding two elements to increase the combined system bandwidth.

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Multiprocessor Packet Switching Memory and I/O Channel

A multiprocessor system with a conventional interconnecting channel achieves much less performance than the same number of processors used in separate uniprocessor systems. This is because a typical processor can use almost the entire bandwidth of the channel and starve any other processors tied to it. This limitation can be overcome by adding two elements to increase the combined system bandwidth.

The figure shows a technique for attaching processor-memory units to a memory and I/O channel. The first element added is a packet switch protocol across the interconnecting channel. For maximum bandwidth this channel is operated synchronously at just below the data transfer "transit and sample" time. Arbitration occurs on a previous cycle concurrent with a previous transfer and the "ACKNOWLEDGE/NOT ACKNOWLEDGE" response on a following cycle concurrent with other bus traffic. The packet switch protocol breaks a read function into two independent bus operations. The first is a request which consists of the transmission of an address to be read and a tag. The tag is a of a read packet is the actual return of the data to the requestor. The significant aspect here is that during the access time of the memory the bus is free for other transfers. A write function consists of a two cycle bus request with the address followed by the data to be written. By designing the memory controller with an input buffer to store the next request while the controller is currently busy, the memory unit will be able to run at its maximum bandwidth' This prevents the memory unit from remaining idle until the bus sends the next request and eliminates the bus turnaround delay common to most conventional ch...