Browse Prior Art Database

Device Adapter

IP.com Disclosure Number: IPCOM000048912D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR

Abstract

A Direct Memory Access (DMA) controller (for example, 8257 of Intel) works with memory devices if the low-order, address bits are multiplexed onto a Data/Address bus.

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Device Adapter

A Direct Memory Access (DMA) controller (for example, 8257 of Intel) works with memory devices if the low-order, address bits are multiplexed onto a Data/Address bus.

The memory devices normally connect to a processor (for example, 8085 of Intel) through an address bus (address bits A8-A15) and a data bus (data bits and, at other times, address bits A0-A7). An 8257 incompatibility is that it normally supplies address bits A8-A15 to the data bus. The 8185 therefore receives the high addresses from the 8257; whereas. to operate correctly, it must receive the low-order addresses.

A buffer (Fig. 2) redirects the high-order address bits A8-A15 from the 8257 to the address bus. While two other buffers redirect the low order address to the system (8185) data bus, an ADSTB signal and an AEN signal generate an ALE indicator. An ADSTB signal enables a high-order buffer and latch to store address bits A8-A15 until the AEN signal releases them to the address bus.

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