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Masterslice Universal Book Design

IP.com Disclosure Number: IPCOM000048914D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Hargrove, MJ: AUTHOR [+2]

Abstract

To improve turnaround time in the manufacture of masterslice logic chips, particularly chips requiring four levels of metal, desired diffusions are made in a semiconductor wafer followed by the formation of a universal book or metal pattern which may be later interconnected through via holes and a second level metal to form one of several different logic functions, such as 4-way AND INVERT, 4-way CDOT, AND EXTEND book and HIGH SPEED RESISTOR book.

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Masterslice Universal Book Design

To improve turnaround time in the manufacture of masterslice logic chips, particularly chips requiring four levels of metal, desired diffusions are made in a semiconductor wafer followed by the formation of a universal book or metal pattern which may be later interconnected through via holes and a second level metal to form one of several different logic functions, such as 4-way AND INVERT, 4-way CDOT, AND EXTEND book and HIGH SPEED RESISTOR book.

A circuit or gate used as a conventional logic cell, which is commonly formed in masterslice logic chips, is illustrated in Fig. 1.

This cell has an input transistor T1 with four input emitters E1, E2, E3 and E4 and a Schottky barrier diode SBD1 connected between its base B and collector C, an output transistor T2 with a Schottky barrier diode SBD2 connected between its base b and collector c and first, second and third resistors R1, R2 and R3, respectively.

Collector C of transistor T1 is shown connectible through a gap or interconnect point G1 to base b of transistor T2. Resistor R1 is connectible through gap G2 to base B of transistor T1, resistor R2 is connectible through gap G3 to collector C of transistor T1, and resistor R3 is connectible through gap G4 to collector c of transistor T2. Output terminals are indicated at 01, 02 and 03.

The circuit or cell of Fig. 1 is shown in Fig. 2 formed on a semiconductor wafer, with the dashed lines indicating diffusions in the wafer and the s...