Browse Prior Art Database

Process for Simultaneously Making Thin and Thick Epitaxial Layers

IP.com Disclosure Number: IPCOM000048919D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Howard, DD: AUTHOR

Abstract

A process is provided for simultaneously producing on a common substrate a thin epitaxial layer on a first portion of the surface of the substrate and a thick epitaxial layer on a second portion of the surface of the substrate for forming low voltage devices and high voltage devices, respectively, on the common substrate.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 83% of the total text.

Page 1 of 2

Process for Simultaneously Making Thin and Thick Epitaxial Layers

A process is provided for simultaneously producing on a common substrate a thin epitaxial layer on a first portion of the surface of the substrate and a thick epitaxial layer on a second portion of the surface of the substrate for forming low voltage devices and high voltage devices, respectively, on the common substrate.

As indicated in Fig. 1, deep trenches 10, e.g., 40 microns deep and 80 microns wide. are formed in a silicon substrate 12 to provide mesas 14. An epitaxial layer 16 of magnesium aluminum spinel is grown over the exposed surfaces of substrate 12 to a thickness of about one micron. An epitaxial layer 18 of silicon is grown on spinel layer 16 having a minimum thickness in excess of the height of the mesas 14. The surface of the epitaxial layer 18 is planarized, by, e.g., grinding and polishing techniques, to a level which provides a three to five micron thickness of the epitaxial layer 18 over the upper surface of mesas 14, as indicated in Fig. 2.

Thin silicon segments 20 in layer 18 disposed over mesas 14 are isolated from thicker silicon segments 22 located in deep trenches 10 by forming openings 24 at the edges or corners of mesas 14 and filling openings 24 with an appropriate dielectric material 26. Openings 24 should be formed so as to at least expose the surface of spinel layer 16.

Any suitable high voltage devices or elements may then be formed in thick silicon segments 22, an...