Browse Prior Art Database

CMOS XOR

IP.com Disclosure Number: IPCOM000048924D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Hiltebeitel, JA: AUTHOR

Abstract

A basic logic building block in complementary metal oxide semiconductor (CMOS) technology is illustrated in the figure as a minimum device inverse exclusive OR (XOR) which does not require direct current power.

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CMOS XOR

A basic logic building block in complementary metal oxide semiconductor (CMOS) technology is illustrated in the figure as a minimum device inverse exclusive OR (XOR) which does not require direct current power.

A voltage source indicated at terminal VH, having a voltage magnitude of preferably 5 volts, is connected to serially arranged first and second transistors 10 and 12, each of which are of the P channel type. Input terminal a is connected to third transistor 14 and input terminal b is connected to fourth transistor 16, each of which are of the N channel type.

In the operation of the circuit, when inputs at both terminals a and b are low,
i. e., indicating a 0 input, transistors 10 and 12 are turned on to provide a high output voltage at terminal 18, indicating a 1 output. When the input at terminal a is low and the input at terminal b is high, transistor 14 is turned on and transistor 10 is turned off, thus the output at terminal 18 is low. With the input at terminal a high and the input at terminal b low, transistor 16 is turned on and transistor 12 is turned off, thus the output at terminal 18 is low. A high input at both terminals a and b turns on both transistors 14 and 16 and turns off both transistors 10 and 12 to provide a high voltage or a 1 output at terminal 18.

Accordingly, with a capacitive load connected to terminal 18, this inverse exclusive OR circuit, using minimum devices, utilizes no direct current power.

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