The Prior Art Database and Publishing service will be updated on Sunday, February 25th, from 1-3pm ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Push/ Pull Data Scan Circuits

IP.com Disclosure Number: IPCOM000048925D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 56K

Publishing Venue


Related People

Griffin, WR: AUTHOR


Data scan circuits are provided which use fewer devices and have a density improvement.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 81% of the total text.

Page 1 of 2

Push/ Pull Data Scan Circuits

Data scan circuits are provided which use fewer devices and have a density improvement.

The circuit in Fig. 1 includes a latch 10 having a first input connected to a first serially arranged circuit of transistors 12 and a second input connected to second and third serially arranged circuits of transistors 14 and 16, respectively. Each of the serially arranged circuits 12, 14 and 16 includes first, second and third N channel transistors T18, T20 and T22, respectively, and a P channel transistor T24, with latch 10 being connected to the common point between transistors T18 and T20 of circuits 12, 14 and 16. The first N channel transistor T18 may preferably be designed as a zero threshold transistor.

In the operation of the circuit of Fig. 1, data is applied to data terminals 1, 2 and 3 and then data is stored in latch 10 by selectively applying a strobe pulse to strobe terminal 1, 2 or 3, depending on the data to be stored in latch 10.

The circuit in Fig. 2 is similar to that of Fig. 1 but uses only N channel transistors in first, second and third serially arranged circuits 12', 14' and 16', with a fourth N channel diode-connected depletion type transistor T24' replacing P channel transistor T24. Additionally, a fifth N channel transistor T26 is connected to a control gate of fourth N channel transistor T24' in each of the circuits 12', 14' and 16' to invert the data applied to transistor T24', achieving the same function as P channel...