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Pipeline Processor Exception Control Mechanism

IP.com Disclosure Number: IPCOM000048954D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Dale, SP: AUTHOR [+4]

Abstract

The occurrence of exceptions in a pipelined operation can cause difficulties with the controls, since an exception may occur for one operation before a previous operation is out of the pipeline. Propagation of the EXCEPTION signal with data will eliminate this problem.

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Pipeline Processor Exception Control Mechanism

The occurrence of exceptions in a pipelined operation can cause difficulties with the controls, since an exception may occur for one operation before a previous operation is out of the pipeline. Propagation of the EXCEPTION signal with data will eliminate this problem.

An initiation signal provided by a sequencer is shifted through the pipeline with the data, so that when the data reaches the result register, the same signal is the VALID DESTINATION signal.

The Multiplier and ALU sections of the pipeline each have pre and post operation stages for alignment, normalization, sign testing, and exception detection. An exception which occurs in the pipeline causes an EXCEPTION signal, and also sets an external register to specify the type of exception.

The EXCEPTION signal propagates through the pipeline with the data and the initiation signal. When the EXCEPTION signal reaches the result register, it nullifies the corresponding VALID DESTINATION signal and all following destination signals in the pipeline. However, it does not affect any previous operations.

This arrangement allows previous operations to be completed before the pipeline is stopped by an exception. It is not necessary to provide extra controls to complete preceding operations still in the pipeline when an exception occurs.

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