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# Design Algorithm For MLC Via Bulge

IP.com Disclosure Number: IPCOM000048966D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 20K

IBM

## Related People

Delia, WM: AUTHOR [+2]

## Abstract

In the design of multilayered ceramic (MLC) substrates the ability to provide microsocket designs that are compatible with device footprints and that are also via bulge controllable is critical. The technique described here provides a design algorithm to accomplish that task.

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Design Algorithm For MLC Via Bulge

In the design of multilayered ceramic (MLC) substrates the ability to provide microsocket designs that are compatible with device footprints and that are also via bulge controllable is critical. The technique described here provides a design algorithm to accomplish that task.

By inputting design parameters into the algorithm, via bulge can be calculated and assessed relative to product and design criteria.

The algorithm is: (SEE ORiginal) where W is the via bulge, X is the number of via layers,

Y is the rows from nearest border, and

Z is columns from nearest border.

The algorithm has been used to compare via bulge for one product's X and Z sites and for another product's sites. The average RMS error was found to be 7.4 percent, and there is an 80 percent confidence level that the error of any given data point is 10 percent or less. The constants are:

A equals -22.6

B equals 0.22

C equals 3.54

D equals 3.69

E equals 14.8

F equals 5.21

G equals 1.36

An interpretation of the model is as follows:

zero bulge).

The Z term provides gradually increasing values to

simulate increasing bulge from edge to center.

The X term provides via layer correction and is the

inverse of

actual design (larger correction for fewer layers).

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