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Enhancing the Performance of Bipolar Transistors

IP.com Disclosure Number: IPCOM000048970D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is disclosed to improve the performance of bipolar transistors of the "poly-base" type which take advantage of a doped polycrystalline layer for contacting the transistor base zone. The preferred process is as follows: 1. Starting with a P- substrate, form N+ 4 and P+ 6 subcollector and subisolation regions, respectively, in a conventional manner. Grow Grow approximately 1-2 Mu m N- epi layer 8, about 100-400 nm thermal SiO(2) 10, and form recessed oxide isolation (ROI) 12 using the agency of Si(3)N(4) also in a conventional manner. Form N+ collector reach-through region 14 using either ion implantation across Si0(2) 10 or conventional diffusion through an opening in SiO(2) 10. followed by re-oxidation.

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Enhancing the Performance of Bipolar Transistors

A method is disclosed to improve the performance of bipolar transistors of the "poly-base" type which take advantage of a doped polycrystalline layer for contacting the transistor base zone. The preferred process is as follows:
1. Starting with a P- substrate, form N+ 4 and P+ 6

subcollector and subisolation regions, respectively,

in a conventional manner. Grow

Grow approximately 1-2 Mu m N- epi layer 8,

about 100-400 nm thermal SiO(2)

10, and form recessed oxide isolation (ROI) 12 using the

agency of Si(3)N(4) also in a conventional manner. Form

N+ collector reach-through region 14 using either ion

implantation across

Si0(2) 10 or conventional diffusion through an opening

in SiO(2) 10. followed by re-oxidation. The transistor

structure at this stage of the conventional processing is

shown in Fig. 1.
2. Deposit polysilicon (poly) 16, about 350-700 nm in

thickness, form a P+

layer 17 at the surface of poly 16 preferably

through ion implantation and create islands in poly 16 using

photolithography. Deposit about 100-150 nm Si(3)N(4) 18

over the entire substrate, preferably at around 800 degrees

C, as indicated in Fig. 2.
3. Using lithography and vertically directional reactive ion

etching (RIE), form patterns in Si(3)N(4) 18 and poly 16,

as shown in Fig. 3.
4. Through controlled selective wet etching or isotropic dry

etching, form about 0.2 - 0.5 Mu m laterally deep

undercuts in poly

16. Next, using selective wet etching or isotropic dry

etching, etch exposed SiO(2) 10 to obtain the structure

shown essentially in Fig. 4.

5. Using the technique of selective epitaxy wherein silicon

film formation is prevented above Si(3)N , grow about

0.18 - 0.48 Mu

m thick layer of silicon 22 - 22 at the surface of

exposed silicon 8 and poly 16. In this process step, the

silicon 22 nucleating from N- epi layer 8 will be

monocrystalline, while

the silicon 22' nucleating from poly 16 will be

polycrystalline. Silicon 22 - 22' forms one contiguous film

at the end of this process step, as depicted in Fig. 5. 6. Diffuse in a P dopant 24 at the surface of silicon 22 - 22'. The P 24 region

meets P+ 17 diffused in poly 16 to form a contiguous P

region, as indicated in Fig. 6. About 0.3 - 0.7 Mu m

thick layer of pyrolytic SiO(2) 26 is deposited and

1

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subsequently removed

excepting its "sidewall" portions, as depicted in

Fig. 6. Vertically directional RIE is preferably used

for this purpose.

7. A window is opened in the Si(3)N(4) 18 / SiO(2) 10

above the collector

reach-through region, and N+ dopant 28 is diff...