Browse Prior Art Database

High Density, High Performance Fet Process and Structure

IP.com Disclosure Number: IPCOM000048976D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Malaviya, SD: AUTHOR

Abstract

The present process produces self-aligned gate, self-aligned field oxide, reduces source and drain capacitances drastically, and reduces gate delay. The process outline is as follows: 1. Provide P-substrate 10, form screen silicon dioxide, deep boron implant for threshold adjustment (optional), and anneal. 2. Strip screen silicon dioxide, regrow gate silicon dioxide 12 for better gate integrity. Grow thin silicon nitride 14, if a composite oxide/nitride gate is desired. 3. Deposit about 3000 angstroms or more of polysilicon 15, then another thin layer, 500 angstroms of silicon nitride 16. 4. Chemical vapor deposit (CVD) polysilicon, about 1 micron thick.

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High Density, High Performance Fet Process and Structure

The present process produces self-aligned gate, self-aligned field oxide, reduces source and drain capacitances drastically, and reduces gate delay. The process outline is as follows: 1. Provide P-substrate 10, form screen silicon dioxide,

deep boron implant for threshold adjustment

(optional), and anneal.

2. Strip screen silicon dioxide, regrow gate silicon

dioxide 12 for better gate

integrity. Grow thin silicon nitride 14, if

a composite oxide/nitride gate is desired.

3. Deposit about 3000 angstroms or more of

polysilicon 15, then another thin layer,

500 angstroms of silicon nitride 16.

4. Chemical vapor deposit (CVD) polysilicon, about 1

micron thick. Then form a third layer of silicon

nitride 18 to produce the Fig. 1 structure.

5. Use a mask to reactive ion etch (RIE) silicon nitride 18

and polysilicon 17, with end-point detect at silicon

nitride.

6. Oxidize the exposed edge of polysilicon 17, using

preferably high

pressure oxidation. The thickness of the resulting

silicon dioxide stud 20 is about 1 micron.

7. Spin on photoresist layer and RIE to expose the

remaining silicon nitride 18, and

and etch the photoresist away. Etch polysilicon

17, leaving free-standing silicon dioxide studs,

one of which is labeled 20 in Fig. 2.

8. Use the stud 20 as a mask to RIE silicon nitride 16 and

polysilcion 15

15 with end-point detect at silicon nitride 14.

9. Thermally oxidize the exposed edges of polysilicon 15 to

1000 angstroms or more.

10. Continue to RIE to a depth of about 1 micron or more

into the silicon substrate 10.

11. Thermally grow about, 500 angstroms silicon dioxide 22,

followed by

about 500 angstroms to 1000 angstroms CVD silicon

nitride 24, and RIE the silicon nitride to

to leave a silicon nitride sidewall 24 covering,

as shown in Fig. 3.

12. Oxidize the exposed horizontal surfaces of the

wafer to a depth of about

3000 angstroms or more to form silicon

dioxide layer 26 and the Fig. 3 structure.

13. Use a mask to etch out silicon nitride 24 and the

silicon dioxide 22

1

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under it chemically from the sidewalls where the source

and drain diffusions are to be made. Diffuse N+ or use

a thin layer of N+ doped polysilicon to accomplish the

diffusion. The source and drain regions 30, 32 are

thus formed in selected areas of

the vertical silicon under the stud 20, as

seen in Figs. 4 and 5.

14. Use another mask to etch silicon nitride 24,...