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Aligning and Error Sorting of Skewed Signals using FIFO Buffers

IP.com Disclosure Number: IPCOM000048977D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Ainsworth, RA: AUTHOR [+2]

Abstract

An arrangement is provided whereby skewed signals are aligned using first in-first out (FIFO) buffers such that both individual system tuning of delay lines and CPU data sorting is eliminated.

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Aligning and Error Sorting of Skewed Signals using FIFO Buffers

An arrangement is provided whereby skewed signals are aligned using first in-first out (FIFO) buffers such that both individual system tuning of delay lines and CPU data sorting is eliminated.

Events A and B (each consisting of multiple bits) typically occur delayed from each other with an unknown and variable skew. The system in such instances may, however, require that A and B be viewed simultaneously. In such an arrangement, each B event, for example, contains error information for the corresponding A event.

The figure shows the FIFO buffer arrangement wherein events A1, A2, A3, A4, etc., are sequentially shifted into FIFO buffer 1, as they occur. At a later time, events B1, B2, B3, B4, etc., are shifted into FIFO buffer 2. Both the A and B events travel through the FIFO buffers and, eventually, events A1 and B1 appear in the respective output registers of the FIFO buffers. This is shown by "output ready" designations on the respective FIFO buffers. The "output ready" signals of buffers 1 and 2 are fed to AND gate 4 whose output is fed to AND gate 3, and the output of AND gate 3 signals subsequent logic circuitry that a sort of events A may now begin.

As shown in the figure, events A, which have a corresponding error indication B, are then shifted into FIFO buffer 5 and thence to the CPU. When the error indication is noted, a "shift in" to FIFO buffer 5 occurs. This is followed by a "shift out" of...