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Current Switch Emitter Follower/ Low Voltage Inverter Receiver Circuit

IP.com Disclosure Number: IPCOM000048985D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Mosley, JM: AUTHOR [+2]

Abstract

The receiver circuit is shown in Figs. 1 and 2. The Low voltage inverter (LVI) circuit portion of the receiver circuit is more fully described in (*) The circuits have the following features: a. Current switch receiver with inputs A, A', A", with threshold at ground potential, and allowing /+/- 0.6 V swings. b. LVI logic circuit with inputs B, B', B", with internal logic LVI voltage threshold, and appropriate voltage swings. c. The interconnection of the current switch emitter follower (CSEF) and LVI circuits provides the following characteristics: Push-pull drive at internal (LVI) levels from both LVI circuit portion and CSEF portion. Logic can be performed on signals coming on chip in the receiving stage.

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Current Switch Emitter Follower/ Low Voltage Inverter Receiver Circuit

The receiver circuit is shown in Figs. 1 and 2. The Low voltage inverter (LVI) circuit portion of the receiver circuit is more fully described in (*) The circuits have the following features:

a. Current switch receiver with inputs A, A', A", with

threshold at

ground potential, and allowing /+/- 0.6 V swings.

b. LVI logic circuit with inputs B, B', B", with internal

logic LVI

voltage threshold, and appropriate voltage swings.

c. The interconnection of the current switch emitter follower

(CSEF) and LVI circuits provides the following

characteristics:

Push-pull drive at internal (LVI) levels from both LVI

circuit portion and CSEF portion.

Logic can be performed on signals coming on chip in the

receiving stage. The circuit is capable of mixing

off-chip signals with on-chip signals to thereby

save a stage of delay. (Consideration must be

given to RC/DSCH design optimization between the CSEF

circuit and the LVI circuit.)

Fig. 1 depicts the receiver circuit with a biphase current switch and emitter follower cooperating with the LVI circuit.

Fig. 2 depicts a dual reference current switch circuit where one device feeds the collector resistor RC and diode DSOH and the other device feeds the emitter of the pull-up transistor. References
(*) John G. Posa, "Low-V inverter logic outperforms ECC

yet saves

power," Electronics 4, 41-42 (February 24, 1981). Also, see

U.S. Patent 4,283,640.

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