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Browse Prior Art Database

Fan-In Capacitance Minimization

IP.com Disclosure Number: IPCOM000048986D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Mosley, JM: AUTHOR [+3]

Abstract

The logic circuit of Fig. 2 has enhanced fan-in capability as compared to the Low Voltage Inverter (LVI) logic circuit of Fig. 1. The LVI logic circuit is described in detail in (*).

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Fan-In Capacitance Minimization

The logic circuit of Fig. 2 has enhanced fan-in capability as compared to the Low Voltage Inverter (LVI) logic circuit of Fig. 1. The LVI logic circuit is described in detail in (*).

Providing an extended fan-in capability detracts from the performance of the circuit since it increases both the collector to substrate capacitance (CCS) and collector to base capacitance (CCB) and additional wiring capacitance due to the additional input devices. The pull-up resistor RV charges all of these capacitors on a positive transition, while a device pulling the node low discharges all of these capacitors.

A solution to this problem is to provide a fixed capacitance for R3 to charge independent of fan-in and to provide a fixed voltage at the fan-in collector node. The fixed voltage eliminates charging and discharging of the CCS and CCB capacitances associated with the additional fan-in.

Fig. 2 shows an implementation of this technique. the additional transistor provides a fixed capacitance for the pull-up resistor R3 and fixes the voltage at the collector node.

This technique is applicable to other logic technologies such as current switch and half current switch, with the limitation that inserting the extra transistor does not saturate the input devices or saturate the extra transistor. References
(*) John G. Posa, "Low-V inverter logic outperforms ECL yet

saves power," Electronics 4, 41-42 (February 1981). Also,

see U.S. Patent 4,283,640.

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