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Active Pull Down Circuit for Current Controlled Gate

IP.com Disclosure Number: IPCOM000048989D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Dansky, AH: AUTHOR [+2]

Abstract

Introduction The disclosed circuit has a lower speed power product than T/2/L (transistor-transistor logic) which is considered the best circuit at present for low power operation (less than 1 mw). The circuit has push-pull drive with negligible DC current in both DC states (on and off). The push pull drive results in an average sensitivity to load capacitance (for an internal circuit with 2.0 V power supply voltage) of .12 ns/pF at .5 mw average circuit power dissipation.

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Active Pull Down Circuit for Current Controlled Gate

Introduction The disclosed circuit has a lower speed power product than T/2/L (transistor-transistor logic) which is considered the best circuit at present for low power operation (less than 1 mw). The circuit has push-pull drive with negligible DC current in both DC states (on and off). The push pull drive results in an average sensitivity to load capacitance (for an internal circuit with 2.0 V power supply voltage) of .12 ns/pF at .5 mw average circuit power dissipation.

The features of the circuit are: (1) elimination of feedback loop from output to collector of input transistor which improves the stability compared to previous versions of the current-controlled gate (CCG), and (2) use of transistor with emitter-base short as a collector-base diode with high capacitance when forward biased to keep T5 (pull-down) OFF when input is low and to capacitively couple the input to T5. Circuit Operation

The circuit schematics are shown in Fig. 1A and 1B with each transistor numbered. Devices 1 and 2 perform the NOR function. Transistor 7 functions as a clamp to prevent devices 1 and 2 from saturating at high temperature and high supply. Transistor 3 functions as the base to collector diode with high capacitance when the input is initially down. Transistors T4 and T5 function as an emitter follower and AC coupled active pull-down device, respectively. First, the DC operation of the circuit will be described.

Referring to Fig. 1A, if either or both of the two inputs are high, then transistors T1 or T2 or both are conducting, causing the voltage at the base of T4 to drop in order to turn T4 off.

The network consisting of R1, R2 and T7 is designed to prevent T1 and T2 from saturating, which at the same time allowing for the complete turning off of T4. A small amount of current through R4, since R4 is very large, provides base drive to yield a down level at the output. The low barrier diode clamp across output device T5 gives an output voltage of about 0.5 volt. Because the inputs are high, the emitters of T1 and T2 are about 0.4 volt above ground (a high level at the input is about 1.2 volts). This means that there is no current across the base collector of T3.

If both inputs are low, then T1, T2 and T7 are off, causing the base of T4 to approach the power supply voltage. T4 behaves as an emitter follower, yielding an output voltage of about (Vcc-Vbe). Since T1 and T2 are both off, and since R4 is much larger than R3, the base voltage of T5 is about equal to a low current forward voltage of the base-collector diode of T3. Since the contact potential o...