Browse Prior Art Database

Low Power Non-Inverting Tri-State Buffer

IP.com Disclosure Number: IPCOM000049000D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+2]

Abstract

The buffer circuit shown in the figure receives and sends TTL-compatible signals (0.6-2.4 V INPUT and 0.5-2.4V OUTPUT) in phase, with a 25 mA drive capability in the down-level. A control input from on-chip (DS (deselect) facilitates dotting of the OUTPUT with other drivers on the bus by converting the OUTPUT to a high-impedance state.

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Low Power Non-Inverting Tri-State Buffer

The buffer circuit shown in the figure receives and sends TTL-compatible signals (0.6-2.4 V INPUT and 0.5-2.4V OUTPUT) in phase, with a 25 mA drive capability in the down-level. A control input from on-chip (DS (deselect) facilitates dotting of the OUTPUT with other drivers on the bus by converting the OUTPUT to a high-impedance state.

When DS is at 0.3 V or less, transistor T10 is off, T11 is ON, and the OUTPUT signal is a powered-up replica of the INPUT, as follows: with the INPUT HIGH, T2 is ON, driving T6 ON, which holds T7 OFF. At the same time T3 is held OFF, allowing T4 and T5 (through R3) to drive the OUPUT HIGH. With the INPUT LOW T2 and T6 are OFF, allowing R4 to drive T7 ON, holding the OUTPUT LOW. At the same time T3 is ON holding T4 and T5 OFF, since T2 is OFF.

When DS is HIGH (approximately1.7 V), T10 is ON, holding T11 OFF, so that T3 is ON, holding T4 and T5 OFF. Also, T10 drives T6 ON, which holds T7 OFF Thus, all OUTPUT devices are OFF, and the OUTPUT is in a high impedance state.

Separation of pull-up and pull-down drive circuitry (via R3 and R4, respectively) allows independent tradeoffs between power and performance for turn-on and turn-off delays. R9 prevents current hogging at the DS input when drivers are tied together at their DS inputs.

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