Browse Prior Art Database

Shift Register Latch Driver

IP.com Disclosure Number: IPCOM000049002D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Diepenbrock, JC: AUTHOR [+3]

Abstract

A design structure called Level Sensitive Scan Design (LSSD) has been described in U.S. Patent 3,783,254. The purpose of LSSD is to enhance testability of complex logic networks. This is achieved by requiring all latches in a given sequential network to be part of shift register latches (SRLs). These SRLs are tied together to form one or more shift registers whose contents are controllable from scan-in primary inputs (PIs) and scan clocks, and observable at scan-out primary outputs (POs). The effect of these SRLs is to provide an equivalent to electrical test points at those locations in the network where the SRLs are placed.

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Shift Register Latch Driver

A design structure called Level Sensitive Scan Design (LSSD) has been described in U.S. Patent 3,783,254. The purpose of LSSD is to enhance testability of complex logic networks. This is achieved by requiring all latches in a given sequential network to be part of shift register latches (SRLs). These SRLs are tied together to form one or more shift registers whose contents are controllable from scan-in primary inputs (PIs) and scan clocks, and observable at scan-out primary outputs (POs). The effect of these SRLs is to provide an equivalent to electrical test points at those locations in the network where the SRLs are placed.

The block diagram of Fig. 1 depicts the implementation of an SRL and a driver circuit.

The circuit in Fig. 2 is a Darlington push-pull driver circuit in which the Latch 1 function is built into the driver circuit rather than preceding it. By configuring Latch 1 as part of the driver circuit, a series latch delay penalty (see Fig. 1) is obviated. Latch 2 (not shown) is external to the driver circuit.

As shown in Fig. 2, the negative feedback path (nodes X and Y) required for latching is part of the Darlington output circuitry (transistor T4, resistor R3 and diode DM).

Transistors T2, T3 and T7, resistors R1 and R2, and Schottky diodes D2, D3, D4, D5 and D6 are all part of the SRL.

Input transistors T1, T2 and T3 can be integrated into one collector bed to reduce silicon area and capacitance appearing at the base of...