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Reference Voltage Generator for Double Density Array using Five Volt Power Supply

IP.com Disclosure Number: IPCOM000049006D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Chen, SC: AUTHOR [+3]

Abstract

In double density array design, there are several kinds of diodes used in the array area. Since the forward voltages VF of some of the diodes get very close to each other, tracking between VF and the reference voltages generated becomes extremely important. The circuit shown in Fig. 1 will provide this desired feature.

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Reference Voltage Generator for Double Density Array using Five Volt Power Supply

In double density array design, there are several kinds of diodes used in the array area. Since the forward voltages VF of some of the diodes get very close to each other, tracking between VF and the reference voltages generated becomes extremely important. The circuit shown in Fig. 1 will provide this desired feature.

In Fig. 1, Dl and D3 are PN junction diodes. D2, D4, D5 and D8 are high barrier Schottky diodes. D6 and D7 are low barrier Schottky diodes, and R3= R4, R6 equals R7.

Since the PN diode is a leaky device, the diodes Dl, D4, D5, D6 and D3, D8 are stacked in such a way as to guarantee all diodes sink the same amount of current. Transistors Q4 and Q5 are PNPs. They are operating in the linear active region and hence can absorb quite a range of voltages. Due to inherent low Beta of the lateral PNP devices, the values of the resistors R2 and R5 can be appreciably reduced. In addition, Q5 can be integrated into diode D3.

By the nature of the circuit, the voltage drop across nodes A and D will be VAD equals 2VHB+VLB+VPN, where VHB, VLB, VPN are the forward voltages of high barrier Schottky, low barrier Schottky and PN junction diodes, respectively at the current level I. Since nodes A, B and C are at the same potential, the voltage drop across nodes E and F will be VEF equals VADVLB- VHB=VHB+VPN, while that across nodes C and H will be VGH=VAD-VHB-VPN equals VHB+VLB. Therefore, VR1 equals VHB +(VHB+ VPN)/2 and VR2 equals VHB+(VHB+VLB)/2.

The advantages of this circuit are:

VR1 and VR2 track well with the array diodes as the

temperature, power supply and process are varied.

The PNP transistor can be integrated into diode D3 to save

area.

Due to the inherent low current gain of PNP...