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Browse Prior Art Database

Low Cost Design for Raw Card Panel Board Testing

IP.com Disclosure Number: IPCOM000049012D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Delignat, J: AUTHOR

Abstract

The device shown above allows printed circuits to be tested without using sophisticated hardware and software support.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

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Low Cost Design for Raw Card Panel Board Testing

The device shown above allows printed circuits to be tested without using sophisticated hardware and software support.

Two shift registers SR1 and SR2 are used to exercise the networks NET of the printed circuit panel.

Each shift register output of SR1 providing the test data is connected to a given network through a node of the network (left side of the drawing). All the other nodes are connected to the shift register inputs of SR2. Register SR1 is used for "short" detection, and register SR2 for "open" detection.

At the beginning of the sequence, all the SR1 outputs are set to zero by a reset pulse. Then register SR2 is preset with the data present at the parallel inputs.

The open circuit detection is done as follows. During register SR2 loading, all nodes are supposed to be zero so that the SR2 contents will be zero (all data bits "0"). Any open circuit will generate a "1" in register SR2. During scan out, once the clock has been released, output latch L1 will capture any bit set to "1".

The clock counter CTR state is recorded in register REG when the first error bit sets latch L1. This register addresses a programmable read-only memory PROM which drives a display to provide the coordinates of the defective node to the operator.

The short detection is made as follows. The serial input of register SR1 is tied to 1. After releasing, the clock pulses will propagate "1's" into the shift register at the clock speed....