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Browse Prior Art Database

Addressing Scheme with Embedded Parity

IP.com Disclosure Number: IPCOM000049019D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emerson, GA: AUTHOR

Abstract

This article relates to the reduction of malfunctions due to single bit addressing errors in the operation of I/O devices.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 68% of the total text.

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Addressing Scheme with Embedded Parity

This article relates to the reduction of malfunctions due to single bit addressing errors in the operation of I/O devices.

Described is a "pseudo parity" system for use in addressing I/O devices in systems where the address bus is wider than needed for the number of devices to be addressed. In such case, the "addresses" are chosen to have an extra bit which is in fact a parity bit though not so treated by the system. As a result, a single bit error in the "address" points to a non-existent destination.

The scheme is transparent to the programmer or other user by proper address selection for all devices and/or device registers. For example, if there are four registers within a device (or four separate devices), normally the device would look at some predefined two bits on the address lines with the resulting codes 00, 01, 10, and 11. In a system with "pseudo parity", this is still the case for selection but now a third bit is also checked. By recoding the register or device addresses as 100, 001, 010, and 111, respectively, there has been, in a sense, parity added to the address. As stated, this is transparent to the user by simply stipulating that the legal addresses are 100, 001, 010, and 111. Any other address combination would be detected as a parity error or illegal address access attempt. The result of this error could be device and/or system configuration dependent but might typically cause an interrupt with the device...