Browse Prior Art Database

Random Access Memory Beamformer

IP.com Disclosure Number: IPCOM000049027D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 5 page(s) / 58K

Publishing Venue

IBM

Related People

Pierce, RD: AUTHOR [+3]

Abstract

In the reception of radiate wave information in a medium, such as long acoustical waves in water, it has been found useful to employ a phase array of sensors to detect the direction of emanation of the source of the acoustical waves. An earlier publication (*) illustrates the commonly known as beamforming. The approach shown in (*) is applicable for a single bit sensor value. The present invention efficiently implements a beamformer operation using 12-bit sensor values with a random access memory.

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Random Access Memory Beamformer

In the reception of radiate wave information in a medium, such as long acoustical waves in water, it has been found useful to employ a phase array of sensors to detect the direction of emanation of the source of the acoustical waves. An earlier publication (*) illustrates the commonly known as beamforming. The approach shown in (*) is applicable for a single bit sensor value. The present invention efficiently implements a beamformer operation using 12-bit sensor values with a random access memory.

Fig. la illustrates a front view of a spherical array of sensors, showing how the spherical array is categorized into rings of equal latitude. Elements occupying lines of equal longitude are termed staves.

As shown in Fig. 1b, the beamformer provides the following interfaces: Input data consisting of 192 parallel bits (16 rings x 12 bits/ring) by 60 serial elements every processing cycle. Vertically-stabilized full-beam output data consisting of 16 parallel bits by 60 serial beams every processing cycle. Computer control input providing vertical beam stabilization data and mode control. Beamformer Functions

The beamformer, shown in Fig. lb, consists of the following functions: input data distribution 2, computer control input 4, 10-beam sector beamformers 6, and output scaler 8. Input Data Distributor

The input data distributor 2 receives 960 (16 rings x 60 elements) 12-bit elements from the input function every processing cycle. The input data is received parallel by ring (16x12) and serial by azimuth (60).

Since the input function and the linear beamformer processing rates are independent, temporary buffers are required (and provided by the input data distribution) to transfer data to the sector beamformers 6 at a processing rate consistent with state of the art technology. 10-Beam Sector Beamformer

Each 10-beam sector beamformer 6 receives 192 parallel bits x 29 serial elements from the input data distribution (IDD) 2 every processing cycle. Ten 21- bit full beams are accumulated every processing cycle and transmitted serially to the output scaler 8.

Each sector beamformer 6 consists of 16 ring element summer (RES) 10 shown in Fig. 5, one address generator 12 shown in Fig. 6 and one stave summer 14. Ring Element Summer

Each RES 10 receives 12 parallel bits x 29 serial elements

from the IDD 2 every processing cycle. Ten partial-beam sums

are generated and transmitted to the stave summer 14. The RES

10 consists of random-access memory (RAM) 16, shown in Fig. 2,

and an arithmetic unit 18 shown in Fig. 5. Selected element

data is transferred into the RAM 16 during a write cycle and

read from the RAM 16 during an accumulation cycle. The

arithmetic unit 18 consists of an adder and register to

1

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provide for partial-beam summation.

Address Generator

The address generator 12 receives vertical stabilization data

from the computer control input 4 and generates the address

control for each independent R...