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Browse Prior Art Database

Bit Addressing for Personalization of a Fused Link PLA

IP.com Disclosure Number: IPCOM000049035D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 74K

Publishing Venue

IBM

Related People

Wu, WW: AUTHOR

Abstract

Personalizing of fused link programmable logic array (PLA) can be accomplished by adding row and column select circuits in the AND and the OR arrays. I. AND Array Personalization A. Row Select There are two approaches: (a) adding a shift register 10 between the AND and the OR arrays, and (b) adding a decoder, which is a diode AND array, between the two arrays. a. Shift Register As shown in Fig. 1, a shift register stage 10 is added to each row of the PLA between each output line of the AND array 12 and the input line of the OR array 14.

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Bit Addressing for Personalization of a Fused Link PLA

Personalizing of fused link programmable logic array (PLA) can be accomplished by adding row and column select circuits in the AND and the OR arrays.
I. AND Array Personalization

A. Row Select

There are two approaches: (a) adding a shift register 10

between the AND and the OR arrays, and (b) adding a decoder,

which is a diode AND array, between the two arrays.

a. Shift Register

As shown in Fig. 1, a shift register stage 10 is

added to each row of the PLA between each output

line of the AND array 12 and the input line of the

OR array 14. Associated with each stage 10 is a

trensistor 16 and a common power supply pin (V(LL1)

A row is selected by placing a binary 1 in stage 10

while a negative supply voltage is connected to the

common pin V(LL1) biasing the sinking transistor 16

on. This provides a path for a large current 18

through the devices 20 and fusing elements 22 to

the sink. The V(LL1) pin is connected only during the

personalization phase.

b. Diode Decoder

As shown in Fig. 2, a diode-array decoder 24 associated

with a sink (Rl, T2)-test (R2. T3, T4) circuit for

each product term can also be used for row selection.

The diode array is a positive AND circuit. When a

particular word is selected, T2 is on (and T4 is off).

Thus. T2 provides a sinking path for the fuse-current.

The PLA-S needs a diode array of 7 inputs and 80

outputs. In front of the diode array, shift latches

can be added and connected in series with the input

latches (I.L.'s) as well as the output latches (O.L.'s)

to form LSSD (level sensitive scan design) for saving

pins.

B. Column Select

Fig. 3 shows a 2-to-4 decoder consisting of 2

phase-splitters and 4 AND

circuits, with a fuse 26 shunting the out-of-phase

side of one of the two splitters. When input A is a 0,

all the outputs of the decoder will be down no matter

if the other input is at "0" or "1".

Now, if the "0"s are applied to all the inputs, none

of the outputs will be

selected. The procedure of personalizing

a bit at a time can be started as follows:

1. Blow the fuse at the first decoder by applying a

power supply at the input; forward-bias the

resistor junction

to provide a path for the fusing current.

1

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2. Select the corresponding row using the row select

techniques described above.

3. Select one column at a time by applying the proper

signals (00, 01, 10 or 11) to the inputs of the

decoder just blown.

4. Apply V(LL1) to blow the fuse in the array cell.

5. Go back to Steps 2, 3 and 4 until all the bits

associated with the first decoder have been

personalized.

6. Blow the fuse of the next decoder.

7. Select the corresponding row, and at the same

time apply the

inputs to the previously blown decoder (in

this case the first decoder) to match the product

term of the corresponding row. (When a row is

matched, those cells at the intersections of the

columns and the row become inactive. That means

there will be no current flowing through the...