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Codes for Accumulated-Error Channels

IP.com Disclosure Number: IPCOM000049038D
Original Publication Date: 1982-Apr-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 58K

Publishing Venue

IBM

Related People

Bederman, S: AUTHOR [+3]

Abstract

An error correction system is provided with an additional bit to each SEC-DED (single error correction-double error detection) code word, that adds the capability to reliably correct double errors consisting of either hard-hard or hard-soft errors. Soft-soft errors are not corrected, but are detected as an uncorrectable error (UE). In the event that a triple error occurs, due to the occurrence of an additional error, either hard or soft, this will be detected as a UE. :AB The correction algorithms which define the operation of the correction hardware take advantage of the fact that the typical bit-slice memory design results in the accumulation of errors in any given word, rather than the instantaneous appearance of multiple errors in any given word. Thus.

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Codes for Accumulated-Error Channels

An error correction system is provided with an additional bit to each SEC-DED (single error correction-double error detection) code word, that adds the capability to reliably correct double errors consisting of either hard-hard or hard-soft errors. Soft-soft errors are not corrected, but are detected as an uncorrectable error (UE).

In the event that a triple error occurs, due to the occurrence of an additional error, either hard or soft, this will be detected as a UE. :AB The correction algorithms which define the operation of the correction hardware take advantage of the fact that the typical bit-slice memory design results in the accumulation of errors in any given word, rather than the instantaneous appearance of multiple errors in any given word. Thus. any given word will acquire first a single error, then a double error, and finally a triple error as time goes by. The coventional strategy following correction is to write good data back into the storage location, and therefore soft errors are made to disappear so that only hard errors are allowed to accumulate. Thus, a word which has a hard-soft double error during a particular fetch will have, after the correction procedure, only a single error due to the hard fail.

An intermittent error can be considered for purposes of this discussion to be an error which appears hard for a portion of time. With this definition of an intermittent error, the correction system to be described will reliably correct all combinations of expected double errors where at least one of the errors is hard at the time the fetch and subsequent execution of the correction procedure are performed.

The expected error characteristics for any given code word are shown in the diagrsm of Fig. 1, Error State Transition Diagram for an Accumulated-Error Channel.

The significance of this error model is that errors are assumed to accumulate in an orderly fashion; the sudden appearance of a double or triple error in a word will not occur. A second feature of this model is that by allowing hard errors to become soft, the performance of the correction system in the presence of intermittent errors can be assessed for all possible accumulated error states. Further refinements could be made if the transition probabilities (that is, the intermittent statistics) were known.

The hardware to implement the double error correction is shown in Fig. 2. The control of the operation is defined in terms of procedure A and the Control Algorithm.

Each code word in memory has an additional bit added to the check bits required for SEC-DED. This added bit in each code word is called the DE bit. When the memory is initialized, all the DE bits are set to 0. When a hard error occurs in the word, the DE bit for that word is set to 1.

Each memory fetch is followed by the standard syndrome

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calculation using the check bit generation and compare logic. The control of the correction following th...