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Modular Buffer Allocation Control Logic

IP.com Disclosure Number: IPCOM000049057D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Haigh, DC: AUTHOR

Abstract

This article describes a way of controlling several data buffers which are being filled (written) and emptied (read) in sequence, when the writing and reading occur asynchronously and/or at different data rates. The logic to control the buffers must indicate which buffers should be written and read next, and must also indicate when no buffers are available for writing or reading. The data in each buffer is treated as a complete entity and no attempt is made to take advantage of known different data rates to allow writing and reading of the same buffer simultaneously. This will allow error recovery procedures to be implemented whereby a write or a read may be retried before declaring a buffer to be full or empty.

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Modular Buffer Allocation Control Logic

This article describes a way of controlling several data buffers which are being filled (written) and emptied (read) in sequence, when the writing and reading occur asynchronously and/or at different data rates. The logic to control the buffers must indicate which buffers should be written and read next, and must also indicate when no buffers are available for writing or reading. The data in each buffer is treated as a complete entity and no attempt is made to take advantage of known different data rates to allow writing and reading of the same buffer simultaneously. This will allow error recovery procedures to be implemented whereby a write or a read may be retried before declaring a buffer to be full or empty.

The logic can handle completely asynchronous completion of the reading and writing processes and will never (even momentarily) incorrectly indicate the availability or non-availability of buffers for writing or reading, except, of course, for temporarily invalid indications caused by normal logic delays which prevent instantaneous change between available and non-available indications. Furthermore, the logic is modular and readily lends itself for expansion to cope with any number of buffers. Because of the regular nature of the logic it is possible to add checking circuits to verify its correct operation, which is not usually feasible with control logic.

For correct operation the logic only requires that no writing or reading take place when it indicates that no buffers are available for that process. The logic requires two inputs: a pulse on one means that the current write process has completed and the associated buffer is now full of valid data, and a pulse on the other means that the current read process has completed and the data in the associated buffer can be overwritten by new data (the buffer is described as being 'empty').

The allocation of which buffer to use for a particular process is handled simply by two modulo N counters, where N is the number of buffers. One of the counters counts the completion pulses of the write process and indicates which buffer the write process must use, and the other counter counts the read process completion pulses to indicate the buffer to be used by the read process. These counters are referred to as the write and read allocation counters.

To indicate the availability of a buffer for each process, two extra counters are used, each counting the completion pulses of the process with which it is associated; these counters count up modulo (N 1), where N is again the number of buffers. Two completely separate counters are used in order to be able to handle completely asynchronous completion pulses from each process. These counters are referred to as the write and read availability counters.

The two availability counters are reset to the same state on power up, or whenever it is known that all the buffers are empty. A comparator compares the sta...