Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Parity Holding for 8-Bit Wide Read Only Store Modules

IP.com Disclosure Number: IPCOM000049060D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Rogers, GS: AUTHOR

Abstract

In many data processors, data integrity is provided by parity checking on bytes of data passing through hardware to detect single errors. The use of 8 bit wide read-only storage (ROS) requires a further ROS module to hold parity bits. This means that for 32K of ROS, any changes to any of the base modules requires changing the parity holding module. The drawing shows how parity holding and checking for 8 bit wide ROS can be implemented without having to change the parity holding module each time any of the base ROS modules need to be changed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Parity Holding for 8-Bit Wide Read Only Store Modules

In many data processors, data integrity is provided by parity checking on bytes of data passing through hardware to detect single errors. The use of 8 bit wide read-only storage (ROS) requires a further ROS module to hold parity bits. This means that for 32K of ROS, any changes to any of the base modules requires changing the parity holding module. The drawing shows how parity holding and checking for 8 bit wide ROS can be implemented without having to change the parity holding module each time any of the base ROS modules need to be changed.

The components comprise a parity generator of 1 bit from 8 bits (similar to 74S-280), a 32Kx1 bit random access memory (RAM) and a 2-way 'exclusive- OR' circuit.

During basic assurance time, the contents of ROS are checked longitudinally (CHECKSUM) and, for each byte of ROS addressed by address B-14, a parity bit is written into RAM at the location pointed to by the 15 address bits.

After basic assurance time is completed, the RAM is placed in 'READ' mode and the data bit is read from the RAM location pointed to by address B-14. This is the correct parity for the byte from the identically addressed location in ROS. A parity integrity test is simply a comparison of the bit read from the RAM with the output of the parity generator for all addresses in the 32K range.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]