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Dual Use of Storage Address Space

IP.com Disclosure Number: IPCOM000049064D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Martin, DG: AUTHOR [+2]

Abstract

In a microprocessor having limited address space, a switch operable at a time when assurance tests are conducted is used to switch in assurance code which shares the same address space as other code not used during assurance.

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Dual Use of Storage Address Space

In a microprocessor having limited address space, a switch operable at a time when assurance tests are conducted is used to switch in assurance code which shares the same address space as other code not used during assurance.

In processors, a percentage (typically 10 percent) of storage space is used to hold code for basic assurance tests (BATs). These BATs are used during 'POWER ON' or 'TEST MODE' routines to carry out functional checks that ensure the machine is operational. The BATs code is invariably implemented in read- only storage (ROS).

Consider a machine with an address space of 64K, for example, a microprocessor with a 16-bit address bus. If 6K of the address space is used for BATs code, then only 58K of storage is available for machine operation. By making the BATs code control a hardware latch in the machine to produce a signal BATs time, any card in the machine that contains storage can use this signal to switch its storage access cycles from one storage area to another even though the address lines to both storage areas are common. The drawing shows one method of implementation. A small amount of BATs code is stored in area C id order to test functional ROS in storage area A before setting the BATs time latch and executing code in ROS B.

In an alternative method of operation, the QATs code in ROS can be written into random-access memory (RAM) and the BATs tests run using the BATs code from the RAM area.

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