Browse Prior Art Database

Self Aligned GaAs MESFET Structure

IP.com Disclosure Number: IPCOM000049079D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Jackson, TN: AUTHOR

Abstract

Self-aligned GaAs metal semiconductor field-effect transistor (MESFET) structures in which the source and drain contacts are used to align a later deposited gate are generally limited by edge resolution of the alloyed source and drain contacts. A process that will yield smaller gate lengths employing gate formation through a hole in a metallized region is set forth in connection with Figs. 1 to 4.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 2

Self Aligned GaAs MESFET Structure

Self-aligned GaAs metal semiconductor field-effect transistor (MESFET) structures in which the source and drain contacts are used to align a later deposited gate are generally limited by edge resolution of the alloyed source and drain contacts. A process that will yield smaller gate lengths employing gate formation through a hole in a metallized region is set forth in connection with Figs. 1 to 4.

Deposit and alloy an ohmic metallization such as Au/Ge on a n-type GaAs layer on a Semi Insulating (SI) substrate.

Mask and ion-mill an opening in the ohmic metallization. Due to the lack of uniformity of alloyed contacts, the ion-milling would penetrate into the n-GaAs in a non-uniform fashion. Therefore, the layer thickness a is chosen to be greater than that required in the finished device. To allow self-alignment, a' must also be larger than the final active layer thickness desired. Where a sufficiently precise lithographic technique is used to form the mask for the ion-milling of the opening in the ohmic metallization, then the distance b can be very small, e.g.,
0.1 1.0 micrometers.

A GaAs etch that undercuts its mask is used. The structure is etched until a'' is equal to the active layer thickness required for the finished device. If a carrier- dependent etch, such as KOH, is used for this purpose, then the etching can be made to terminate automatically with a'' determined by bias conditions.

A gate metal is deposited through th...