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Browse Prior Art Database

Reduction Of Punchthrough In Josephson Latching Circuits

IP.com Disclosure Number: IPCOM000049082D
Original Publication Date: 1982-May-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR

Abstract

In Josephson device circuitry, a condition known as punchthrough can occur. In this condition, a Josephson device may not reset when the gate current through it goes through zero. This article describes a technique for reducing the probability of punchthrough by using two or more Josephson devices having uncorrelated phases, the Josephson devices being interconnected by small resistors. This circuit effectively reduces the load impedance as seen by the Josephson devices and thereby reduces their punchthrough probabilities.

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Reduction Of Punchthrough In Josephson Latching Circuits

In Josephson device circuitry, a condition known as punchthrough can occur. In this condition, a Josephson device may not reset when the gate current through it goes through zero. This article describes a technique for reducing the probability of punchthrough by using two or more Josephson devices having uncorrelated phases, the Josephson devices being interconnected by small resistors. This circuit effectively reduces the load impedance as seen by the Josephson devices and thereby reduces their punchthrough probabilities.

To assure acceptably low probability of punchthrough, two factors are required. The first is that there must be sufficient time between +/- I(min) to assure that the V(min) of the gate current exceeds I(min) in the opposite polarity. The second consideration requires that sufficient time between +/- I(min) must be available so that with a very high probability a Josephson device "hung up" in a metastable state would reset to a stable state. Since the time spent between +/- I(min) adds to the cycle time of the digital system, it is desirable to reduce this time. There are various ways of achieving this reduction such as low device capacitances, lower load resistors, etc. However, these solutions either demand improved fabrication technology or adversely affect the circuit performance. In the technique to be described here, the dwell requirement is reduced by a large factor without adversely impacting...